Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. Memory devices that do not lose the data content of their memory cells when power is removed are generally referred to as non-volatile memories. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. A typical floating gate memory cell is fabricated in an integrated circuit substrate and includes a source region and a drain region that is spaced apart from the source region to form an intermediate channel region. A floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the other cell elements by a dielectric material, typically an oxide. For example, gate oxide can be formed between the floating gate and the channel region. A control gate is located over the floating gate and is also typically made of doped polysilicon. The control gate is electrically separated from the floating gate by another dielectric layer. Thus, the floating gate is “floating” in dielectric so that it is insulated from both the channel and the control gate. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively. Other types of non-volatile memory include, but are not limited to, Polymer Memory, Ferroelectric Random Access Memory (FeRAM), Ovionics Unified Memory (OUM), and Magnetoresistive Random Access Memory (MRAM).
Yet another type of non-volatile memory is a Flash memory. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate or charge trapping layer embedded in a field effect transistor (FET) transistor. The cells are usually grouped into sections called “erase blocks.” Each of the cells within an erase block can be electrically programmed selectively by tunneling charges to the floating gate. The negative charge is typically removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation. It is noted that in recent Flash memory devices multiple bits have been stored in a single cell by utilizing multiple threshold levels or a non-conductive charge trapping layer and storing data trapped in a charge near each of the sources/drains of the memory cell FET.
Two common types of Flash memory array architectures are the “NAND” and “NOR” architectures, so called for the resemblance which the basic memory cell configuration of each architecture has to a basic NAND or NOR gate circuit, respectively. In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are connected by rows to word select lines (word lines) and their source/drains are connected to column bit lines and/or source lines. A NAND array architecture also arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are connected by rows to word lines. However each memory cell is not directly connected to a source line and a column bit line. Instead, the memory cells of the array are arranged together in strings, typically of 8, 16, 32, or more each, where the memory cells in the string are connected together in series, source to drain, between a common source line and a column bit line. A memory cell of the NAND architecture floating gate memory array is then accessed by activating a row of floating gate memory cells coupled to the selected memory cell by selecting the word select line connected to their gates. In addition, the word lines connected to the gates of the unselected memory cells of the string are also driven (at a higher voltage) to place them in a pass through mode to allow access to the selected memory cell.
Common programming technique for Flash memories programs a row (a page) of the memory by applying a programming voltage or series of programming voltage pulses to the control gates and programming or inhibiting the selected memory cells to either program (set at logical “0”) or inhibit (not program, usually intended to leave cell erased and set at logical “1”). These programming voltages and/or pulses are typically set by the design and, in certain cases, are trimmed or selected during the manufacturing process, further increasing manufacture costs. However, due to manufacturing process variations from chip to chip, or even from region to region or row to row of a memory array, not every Flash memory or Flash memory cell will program the same for a given applied programming voltage. In addition, even where the programming voltages are selected during manufacturing for the individual memory device the programming characteristics of the memory device can change after multiple program/erase cycles, or changes in supply voltage or temperature.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative methods of programming Flash memory arrays.